#Verilog
Showing 23 of 23 repositories tagged #verilog, ranked by stars
PlatformIO IDE for VSCode: The next generation integrated development environment for IoT
:seedling: Open source ecosystem for open FPGA boards
Veryl: A Modern Hardware Description Language
The OpenPiton Platform
SystemVerilog language server
SystemVerilog parser library fully compliant with IEEE 1800-2017
Verilog/SystemVerilog support for VS Code, including syntax highlighting, snippets, formatting, linting, project-aware navigation, hierarchy, and diagnostics.
A modern and open-source cross-platform software for chips reverse engineering.
Open source software for chip reverse engineering.
An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
A nicer HDL.
A Python library for working with logic networks, synthesis, and optimization.
Convolutional Neural Network RTL-level Design
Generic CNC firmware and driver for FPGA cards which are supported by LiteX
A project dedicated to developing a hardware Integrated Circuit (IC) for a Spike Neural Network (SNN), powered by the RTL code generated by ChatGPT-4 with advanced optimizations.
Minimal TPU implementation with 8x8 systolic array and PyTorch integration
The SpinalHDL design of the Proteus core, an extensible RISC-V core.
Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator
A fast, practical SystemVerilog LSP for RTL coding.
使用 VSCode 舒适地开发 Verilog
ReducedLUT: Table Decomposition with "Don't Care" Conditions [FPGA'25]
Verilog Convolutional Neural Network on PYNQ