#Systemverilog

chipsalliance

verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

veryl-lang

veryl

Veryl: A Modern Hardware Description Language

dalance

svls

SystemVerilog language server

dalance

sv-parser

SystemVerilog parser library fully compliant with IEEE 1800-2017

mshr-h

vscode-verilog-hdl-support

Verilog/SystemVerilog support for VS Code, including syntax highlighting, snippets, formatting, linting, project-aware navigation, hierarchy, and diagnostics.

KastnerRG

cgra4ml

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

suoto

vim-hdl

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

Harry-Chen

fpga-virtual-console

VT220-compatible console on Cyclone IV EP4CE55F23I7

lazyverilog

LazyVerilog

A fast, practical SystemVerilog LSP for RTL coding.