#Modelsim

mshr-h

vscode-verilog-hdl-support

Verilog/SystemVerilog support for VS Code, including syntax highlighting, snippets, formatting, linting, project-aware navigation, hierarchy, and diagnostics.

suoto

vim-hdl

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)