#Riscv
Showing 34 of 34 repositories tagged #riscv, ranked by stars
A simple and easy-to-use library to enjoy videogames programming
ncnn is a high-performance neural network inference framework optimized for the mobile platform
Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)
Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86.
Tengine is a lite, high performance, modular inference engine for embedded device
A fully compliant RISC-V computer made inside the game Terraria
Rust version of THU uCore OS. Linux compatible.
A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host
oreboot is a fork of coreboot, with C removed, written in Rust.
Unix-like OS in Rust inspired by xv6-riscv
RISC-V Supervisor Binary Interface (RISC-V SBI) library in Rust; runs on M or HS mode; good support for embedded Rust ecosystem. For binary download see prototyper folder.
An embedded development environment for mcs51/stm8/avr/cortex-m/riscv on VsCode.
RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).
A Tool to make Build and Run eBPF programs easier
RISC-V processor emulator written in Rust+WASM
Minimalist, dependency-free virtual machine sandbox for microcontrollers and other resource-constrained devices. Single C file, no dynamic memory allocations, asynchronous design, pure C99
A deep learning-powered visual navigation engine to enables autonomous navigation of pocket-size quadrotor - running on PULP
a game where you're given a potato and your job is to implement a firmware for it
CKB's vm, based on open source RISC-V ISA
A modern webapp to write, run and learn M68K, MIPS, RISC-V, X86 assembly
Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
Assured confidential execution (ACE) implements VM-based trusted execution environment (TEE) for embedded RISC-V systems with focus on a formally verified and auditable firmware.
A no_std-friendly ELF loader and runtime linker for Rust
An optimized neural network operator library for chips base on Xuantie CPU.
A kernel written in Rust
Emulador Genérico do Gabriel
Lup Yuen's Articles and Resume
The SpinalHDL design of the Proteus core, an extensible RISC-V core.
This repository lists some awesome public Rust projects, Videos, Blogs and Jobs.
Ultra high-performance secp256k1 ECC engine | Python, Node.js, Rust, Go, C#, Swift, Java bindings | CUDA, Metal, OpenCL GPU | ECDSA, Schnorr, FROST, MuSig2, BIP-352 | 15+ platforms
Example projects for the IAR RISC-V Evaluation Board
A FREE comprehensive step-by-step embedded RISC-V hacking tutorial covering RISC-V Embedded Software Development to Reverse Engineering.
Hardware Hacking CTF hcon2026hwctf - RISCV Hazard3 (@Wren6991) Exploiting by @b1n4ri0 @antoniovazquezblanco & @therealdreg
Cross-compilation build system for creating portable, statically-linked debugging and network tools