#Risc-v
Showing 42 of 42 repositories tagged #risc-v, ranked by stars
A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM, 8-bit AVR and 32-bit RISC-V architectures.
Speech-to-text, text-to-speech, speaker diarization, speech enhancement, source separation, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, HarmonyOS, Raspberry Pi, RISC-V, RK NPU, Axera NPU, Ascend NPU, x86_64 servers, websocket server/client, support 12 programming languages
Your Gateway to Embedded Software Development Excellence :alien:
A secure embedded operating system for microcontrollers
OS kernel labs based on Rust/C Lang & RISC-V 64/X86-32
A fully compliant RISC-V computer made inside the game Terraria
RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.
Let's write an OS which can run on RISC-V in Rust from scratch!
Run a 1-billion parameter LLM on a $10 board with 256MB RAM
A book about how to write OS kernels in Rust easily.
RISC-V processor emulator written in Rust+WASM
Bao, a Lightweight Static Partitioning Hypervisor
a game where you're given a potato and your job is to implement a firmware for it
Detect CPU features with single-file
Nyxstone: assembly / disassembly library based on LLVM, implemented in C++ with Rust and Python bindings, maintained by emproof.com
🚀 A powerful multi-platform RF toolbox that deploys specialized radio, hardware, and other security tools in seconds on Linux, Windows, and macOS - supporting x86_64, ARM64 (Raspberry Pi, Apple Silicon), and RISC-V architectures without disrupting your primary OS. 📡✨
Modular Unix-like 64-bit kernel
A modern webapp to write, run and learn M68K, MIPS, RISC-V, X86 assembly
ncnn benchmark on various single board computers
Pico Pico - Embedded Rust Programming with Raspberry Pi Pico 2
A concise explanation of Rust types and Memory Layout.
An optimized neural network operator library for chips base on Xuantie CPU.
RISC-V kernel implemented with Rust
BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/
Stack-based arbitrary-precision integers - Fast and portable with natural syntax for resource-restricted devices.
Immutable.Friendly.Secure — Reliable embedded Linux for any device
Emulador Genérico do Gabriel
MultiZone® Security TEE is the quick and safe way to add security and separation to any RISC-V processors. The RISC-V standard ISA doesn't define TrustZone-like primitives to provide hardware separation. To shield critical functionality from untrusted third-party components, MultiZone provides hardware-enforced, software-defined separation of multi
Reverse engineering the B5300 CarPlay / Android Auto display!
This is the main repo for Penglai.
Productivity tool for populating an IAR Embedded Workbench project
Tiny RISC-V machine code monitor written in RISC-V assembly.
The SpinalHDL design of the Proteus core, an extensible RISC-V core.
Build embedded applications with the IAR Build Tools on Containers
Tool for converting PyTorch models into raw C codes with minimal dependency and some performance optimizations.
A CI workflow using IAR Build Tools, Jenkins and Gitea in Docker containers
Example projects for the IAR RISC-V Evaluation Board
A FREE comprehensive step-by-step embedded RISC-V hacking tutorial covering RISC-V Embedded Software Development to Reverse Engineering.
Hardware Hacking CTF hcon2026hwctf - RISCV Hazard3 (@Wren6991) Exploiting by @b1n4ri0 @antoniovazquezblanco & @therealdreg
Docker image for RISC-V 32/64 development environment, along with Qemu
Researching next-gen blockchain architecture (as of 2026) to achieve ultimate scalability in permissionless setting and fully resolve Blockchain Trilemma
Binary Editor